Résumé
Yuxuan Chen
Structural Design & Multiphysics Simulation Engineer
Based in Yokohama, Japan
Download PDFExperience
May 2025 – presentJapan
Power Module Structural Design & Simulation Engineer
Power electronics (modules for EV and PV inverters)
- Developed structures for two power modules and two prototype builds; released 50+ part and assembly drawings
- Built coupled thermal-flow-electrical-stress models in COMSOL for 10+ formal simulation cases; 100+ structural iterations
- Broke down power loops to find high-inductance regions; optimized busbars, clips and chip layouts
- Designed a prototype test PCB in KiCad; introduced four fixture sets and wrote assembly SOPs
Projects
Compact Single-Phase SiC Half-Bridge Power ModuleHigh-power-density inverter · Co-optimizing structure, heat and inductancePower-loop parasitic inductance ≈ 7 → 3 nHThermal resistance ≈ 0.15 → < 0.10 K/W
Problem and constraints
Eight SiC MOSFETs had to fit in a module of about 72 mm × 37 mm while lowering both power-loop parasitic inductance and thermal resistance within packaging and assembly constraints.
Method and decisions
Designed the AMB, clips, terminals, busbars, pin-fins and case. Shortened the current loop and stacked the positive and negative busbars for field cancellation; adjusted chip layout and cooling together; compared options with thermal-flow and parasitic-inductance simulation, trading off power density, inductance and thermal resistance.
Results and validation
Parasitic inductance fell from about 7 nH to about 3 nH and thermal resistance from about 0.15 K/W to below 0.10 K/W. Simulations were correlated against prototype measurements; results met the design targets and fed the next structural iterations.
Personal contribution
Structural design and thermal-flow and parasitic-inductance simulation; design reviews and prototype builds were carried out with the team.
Related work: L1 SiC half-bridge power module (generic teaching model, not the actual product). Further reading: S2 Busbar Joule heating, S3 Pin-fin cold plate.
Project metrics
- Power-loop parasitic inductance
- ≈ 7 → 3 nH
- Stacked busbars, shorter commutation loop
- Thermal resistance
- ≈ 0.15 → < 0.10 K/W
- Chip layout and pin-fin cooling optimization
800 V 6-in-1 Three-Level Power ModulePV inverter · Lower loop inductance with stacked busbarsLong-loop inductance 24 → 14 nHShort-loop inductance 18 → 8 nH
Problem and constraints
In an 800 V, 6-in-1 neutral-point-clamped three-level module for PV inverters, multiple long commutation paths made parasitic inductance a direct driver of switching overshoot and loss.
Method and decisions
Independently designed the AMB layout, clips, terminals, busbars and case; implemented the chip layout and cooler in CAD after team discussion. Lowered loop inductance with stacked positive and negative busbars, field cancellation and current-path optimization.
Results and validation
Long-loop inductance 24 → 14 nH (about 42%) and short-loop inductance 18 → 8 nH (about 56%). Completed parasitic-inductance modeling, supplier DFM, prototype builds and electrical-test follow-up; measurements followed the simulated trends.
Personal contribution
Core structural design done independently; chip layout and cooling concept agreed in team discussion and implemented in CAD by me.
Project metrics
- Long-loop inductance
- 24 → 14 nH
- about −42%
- Short-loop inductance
- 18 → 8 nH
- about −56%
Jul 2023 – Apr 2025China
NPI & Field Application Engineer
Automotive optics
- Led ghosting, MTF and cosmetic yield improvements (see the project below)
- Planned processes from assembly to packaging and transport; SOPs, Control Plans, PFMEAs and 8D reports; automated assembly line accepted at 98% yield
- Designed inspection, dispensing and lens-assembly fixtures; supported Japanese customers in Japanese
Projects
Automotive Lens Yield ImprovementEVT–DVT · Root-cause analysis and process improvementGhosting yield 80 → 95%MTF yield 60 → 80%Cosmetic yield 80 → 95%
Problem and constraints
During EVT–DVT, ghosting, MTF and cosmetic yields were low; root causes had to be found and the process stabilized with the design essentially frozen.
Method and decisions
Used part swaps, rotation tests, teardown and DOE to find root causes — spacer interference and thickness variation, lens decenter and tilt, press-fit force and adhesive volume — and drove tolerance, structure, process and incoming-inspection changes; designed and introduced inspection, dispensing and lens-assembly fixtures.
Results and validation
Yields rose from 80% to 95%, 60% to 80% and 80% to 95%. About 50,000 lenses were validated; two trial runs after the changes shipped about 20,000 lenses with yields consistent with validation.
Personal contribution
Led all three improvements; wrote SOPs, Control Plans, PFMEAs, process flow charts and 8D reports; supported Japanese customer meetings and equipment reviews in Japanese.
Related work: L2 Automotive camera lens (generic teaching model, not the actual product).
Project metrics
- Ghosting yield
- 80 → 95%
- MTF yield
- 60 → 80%
- Cosmetic yield
- 80 → 95%
- Validated on about 50,000 lenses; about 20,000 shipped from two trial runs after the changes
Feb 2023 – Jun 2023China
Mechanical Design Engineer (Intern)
Smartphones
- Designed waterproof foam, battery-cover components and SIM trays; maintained PLM drawings
- PCB-mounted nut detachment: switched OSP to ENIG; validation-batch defects 32/100 → 0
Education
Sep 2019 – Jun 2023
Nanchang University
B.Eng., Mechanical Design, Manufacturing and Automation
- One first-class and three second-class scholarships
- Bachelor's project: object recognition and navigation for a quadruped robot with a ZED stereo camera (95% distance accuracy, 0.47° mean yaw error)
Skills
- Mechanical designCATIA, Creo, SolidWorks, AutoCAD; GD&T, tolerancing, materials and finishes, DFM
- Multiphysics simulationCOMSOL heat transfer, laminar flow, Joule heating, thermal stress, non-isothermal flow
- Power modulesAMB, clips, terminals, busbars, pin-fins, cases; parasitic-inductance analysis; KiCad test PCBs
- Prototyping & qualityfixtures and SOPs, first-article inspection, DOE, PFMEA, Control Plans, 8D, root-cause analysis
Languages
- Chinese (native)
- Japanese (JLPT N2, 2022)
- English (TOEFL iBT 100, 2022)