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S2 · SIMULATION

Busbar Joule heating

DC conduction and steady heat conduction in the L1 half-bridge P layer, AC link and N layer

Peak conductor temperature Tmax

114.6°C

Hotspot: AC link · Rise 44.6 K

Joule loss
10.24W
Equivalent resistance
0.256mΩ
Explore parameters
Static preview of the default-case temperature field in the P layer, AC link and N layer
Temperature°C
70.0114.6

FEM-surrogate field (POD reconstruction) interpolated on display lattice points.

Geometry 1:1. The cutaway is a horizontal section below the laminated plates, exposing the AC link and the N riser strap.

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Loss breakdown

10.24 W

Explore parameters

Current is DC or low-frequency RMS. T_sub is the substrate temperature at the soldered pins and also the convection reference.

200
50A400
70
40°C100

Current path

Topology follows the switching state

DC+P layerDC−N layerACACSHSL

DC+ → P layer → S_H → AC link → AC

AC → AC link → substrate 2 → S_L → N layer → DC−

No P-to-N shoot-through (short-circuit) case is calculated.

I / (b·t) = 83.3 A/mm²

Boundary conditions and assumptions

  • Electrical: the terminal bolt-washer face is the equipotential current inlet; the soldered pin or source-clip faces of the conducting switch are the equipotential return; other surfaces are insulated.
  • Thermal: every soldered pin and clip face is held at T_sub; other exposed surfaces convect with h to T∞ = T_sub; conduction into external cables is neglected.
  • The three conductors are solved separately; conduction between them through the insulation film or air is neglected. Dies carry no loss, so clip faces are also held at T_sub.
  • Geometry is read from the L1 parameter file; when t grows, the layers move up with the L1 interlayer clearances.
R = R_g(t, b) / σP = I² RT − T_sub = I² R_g² Θ(t, b, h/k) / (σ k)

R_g and Θ come from the FEM-trained surrogate; current, σ and k scale exactly for constant properties.

Conductors

P layerP 层

Role
Distributes current from the DC+ terminal to the high-side substrate drain copper.
Features
Laminated with the N layer across an insulation film to form a low-inductance busbar; soldered to substrate 1 through a feed foot and post.
Common materials
Oxygen-free or electrolytic copper sheet, nickel or tin plated

AC linkAC 连接片

Role
Joins the high-side sources, the low-side drain and the AC terminal to form the half-bridge midpoint.
Features
A collector bar rests on the four high-side source clips and a narrow bridge strap reaches the substrate 2 drain copper; it carries load current in both switching states.
Common materials
Stamped copper strip or copper alloy, nickel plated

N layerN 层

Role
Collects the low-side source current and returns it to the DC− terminal.
Features
Its collector bar rises around the P-layer edge through a riser strap to the upper laminated plate.
Common materials
Oxygen-free or electrolytic copper sheet, nickel or tin plated

FEM-trained surrogate

Offline self-written finite elements (trilinear hexahedra): the electric potential is solved first, then steady conduction with the Joule heat as its source (sequential coupling). Gaussian-process scalars and POD fields are trained on samples of geometry (t, b) and h/k; the browser only evaluates the surrogate.

Chip losses, skin and proximity effects, the temperature coefficient of resistivity and radiation are excluded. Parametric illustrative model with simplified geometry; results are teaching estimates, not device ratings.

Validation status

Analytical checks: straight-bar R = ρL/A and 1-D conduction rise within 0.4%. Mesh convergence (three nested refinements): the production mesh is within 1.5% of the extrapolated reference resistance and 1.2% of the peak rise. Independent surrogate test (60 cases): peak-rise mean / max error 0.12% / 1.7%, equivalent resistance 0.02% / 0.07%; geometry-grouped 5-fold cross-validation peak rise mean / 95th percentile 0.24% / 1.3%, with the 13.8% maximum from extrapolating to a held-out (t, b) corner. No experimental validation.